The present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device for preventing discordance of a signal timing, which occurs as a chip size and the number of banks are increased in the semiconductor memory device, between data type of signals and command type of signals.
FIG. 1 illustrates a block diagram showing a semiconductor memory device having eight banks. As capacity of a semiconductor memory device is increased and a semiconductor memory device having high-performance, e.g., a double data rate 3 (DDR3) ram, is developed, a bank structure of the semiconductor memory device has been changed from a conventional 4-bank structure to an 8-bank structure shown in FIG. 1.
Generally, a data input/output pad is called a DQ pad and an address and command pad is called an AC pad. At a writing operation, a data is transferred from the DQ pad to a bank and a writing command is transferred from the AC pad to the bank.
As shown in FIG. 1, the DQ pads and the AC pads are placed together in one part of a chip. Therefore, according to a position of each bank, the bank is far from the DQ pad or near the DQ pad. Likewise, the bank is far from the AC pad or near the AC pad.
In case of a sixth and an eighth banks BANK5 and BANK7 marked as DQ worst and CMD (command) best, the banks are far from the DQ pad and near the AC pad. On the other hand, in case of a first and a third banks BANK0 and BANK2 marked as DQ best and CMD worst, the banks are near the DQ pad and far from the AC pad.
FIG. 2 illustrates a signal timing diagram depicting a writing operation at the bank. The upper diagram shows the fastest PVT (process, voltage and temperature) conditions at the position of DQ best and CMD worst. Herein, under the fastest PVT condition, the process tends to fast factors of characteristics and the voltage is high and the temperature is low so that a circuit can have the characteristics of highest operational speed. On the contrary, the lower diagram shows the slowest PVT conditions.
A data to be written in a bank is transferred from the DQ pad to the bank. The transferred data is written in the bank by a bank writing enabling signal BWEN. A column selection signal YS is selected by a column address. The data is written in a memory cell coupled to a column selected while the column selection signal YS is a high level. Herein, the column selection signal YS should become a high level almost at the same time when the bank writing enabling signal BWEN becomes a high level. Therefore, when the bank writing enabling signal BWEN is advanced or delayed, the column selection signal YS should be moved together with the writing enabling signal BWEN.
Meanwhile, for explaining the Data(GIO), generally, the number of logic gates through which a data is transferred to a bank is minimized so that the data has a minimum delay time. However, the data is passed through a long wire line to be transferred to the bank. The long wire line is called a global input/output (GIO) line. The GIO line has the characteristics of RC delay and variation of its characteristics at the fastest PVT conditions and the slowest PVT conditions is small. The data passed through the GIO line, i.e., Data(GIO), is classified into a data type of signal. The tGIO indicates a timing difference of the data type of signal due to the PVT variation.
On the contrary, the bank writing enabling signal BWEN and the column selection signal YS are passed through relatively large numbers of logic gates including a timing circuit and complicated control circuits. Thus, the bank writing enabling signal BWEN and the column selection signal YS are sensitively varied according to the PVT variation. Such signals are classified into a command type of signal. The tCMD indicates a timing difference of the command type of signal due to the PVT variation. As shown, the tCMD is larger than the tGIO.
For the data to be written in the bank, the data should arrive earlier than the command and an appropriate timing margin (tMARGIN) should be secured. Generally, under the fastest PVT conditions, the command type of signal which is sensitive to the PVT variation is faster than the data type of signal. Therefore, in this case, the command type of signal is delayed for the purpose of securing appropriate timing margin. Particularly, under the fastest PVT conditions at the position of DQ worst and CMD best as shown in the upper diagram, the command type of signal is transferred at highest speed. In this case, it is needed to delay the command type of signal.
Meanwhile, under the slowest PVT conditions and the position of DQ best and CMD worst as shown in the lower diagram, the speed of the command type of signal is lowest. Since the data type of signal is not much influenced by the PVT variation and the position is DQ best, the data type of signal arrives at the bank relatively early in spite of the slowest PVT condition.
On the contrary, the command type of signal arrives very late. That is, with the position of CMD worst, the delay amount applied to the command type of signal for securing the appropriate time margin is increased under the slowest PVT conditions.
The column selection signal YS becomes a high level as a pulse not only at the writing operation but at a reading operation. According to the reading operation, a data of a bank is transferred to the GIO line. Herein, since the column selection signal YS is delayed as above-mentioned, a tAA is increased. Herein, the tAA is a performance index for showing how fast a data can be outputted from a reading command. The tAA is an important value for determining a performance of a semiconductor memory device.